1. Technical Field
The present invention relates to a cache memory apparatus for reading data at high speed for use with an information processing unit such as a microprocessor (hereinafter referred to as an MPU).
2. Related Art
Cache memory apparatuses have been widely used to improve the processing speeds of information processing units. The technologies of the cache memory apparatuses are described in, for example:
(1) Harold S. Stone, "High Performance Computer Architecture (Translated Title)", Mar. 30, 1989, Maruzen, pp. 23-42. PA1 (2) Nikkei Electronics [434], Nov. 16, 1987, Nikkei BP Company, pp. 159-174.
In the documents 1 and 2, the basic constructions of conventional cache memory apparatuses are described. The conventional cache memory apparatus includes a memory having a smaller storage amount than an external memory so as to increase processing speeds. This memory is referred to as a cache memory. When data that is often read is stored in the cache memory, this data can be quickly read. When required data is not stored in the cache memory, it is read from an external memory of the cache memory apparatus. The required data is then read at a normal speed. Next, a practical construction of the cache memory apparatus and an operation thereof will be described.
FIG. 2 is a schematic diagram showing a basic circuit of a conventional cache memory apparatus.
In FIG. 2, reference numeral 50 is a cache memory apparatus. The cache memory apparatus 50 outputs cache data CD to a data read requester 1 (hereinafter, the data read requester is referred to as a cache requester) such as a central processing unit according to a cache address CA requested thereby.
The cache memory apparatus 50 comprises a control circuit 10, a cache tag memory 11, a cache data memory 12, and an accordance determining circuit 13. The control circuit 10 controls inner circuits of the cache memory apparatus 50. The cache tag memory 11 is constructed of a small-capacity, high-speed random access memory (hereinafter referred to as RAM) or the like. The cache data memory 12 is also constructed of a RAM or the like. The cache tag memory 11 stores part of addresses of data stored in the cache data memory 12. The cache tag memory 11 has an address terminal A, a data input/output terminal D (hereinafter referred to as an I/O terminal), a write enable terminal WE, and terminals VAi and VAo. The write enable terminal WE is activated by the control circuit 10. Likewise, the terminals VAi and VAo are activated by the control circuit 10. The cache data memory 12 stores data that is often read. The cache data memory 12 has an address terminal A, an I/O terminal D, and a write enable terminal WE. The write enable terminal WE is activated by the control circuit 10. The accordance determining circuit 13 has an enable terminal E. When the enable terminal E is activated, the accordance determining circuit 13 detects whether or not two information accord with each other. When the two information accord with each other, the accordance determining circuit 13 outputs a hit signal HIT.
The cache memory apparatus 50 also comprises registers 14 and 15, an external register 16, tri-state buffers 17, 18, 20, and 21, an AND gate 19, and an IA bus 22. The register 14 has an enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 14 stores a cache address CA. The register 15 also has an enable terminal E. When the enable terminal E is activated with a hit signal HIT, the register 15 stores cache data CD that is received through an ID bus 23. The external register 16 has a count enable terminal CE. When the count enable terminal CE is activated by the control circuit 10, the external register 16 stores an address EA. The tri-state buffers 17, 18, 20, and 21 are controlled by the control circuit 10.
Address terminals A of the cache tag memory 11 and the cache data memory 12 are connected to the output side of the register 14, which stores a cache address CA, through the tri-state buffer 17 and the IA bus 22. The register 14 outputs the number of bits a of a cache address CA to the IA bus 22. Log.sub.2 (the number of tags)=b of the number of bits a is supplied to the address terminal A of the cache tag memory 11. The low order portion (b+1) {where 1=Log.sub.2 (the number of lines)} of the cache address CA is supplied to the address terminal A of the cache data memory 12. The high order portion (a-b-1) of the cache address CA is supplied to both the I/O terminal D of the cache tag memory 11 and the accordance determining circuit 13. The terminal VAo of the cache tag memory 11 is connected to the enable terminal E of the accordance determining circuit 13 through the AND gate 19, which is controlled by the control circuit 10.
The I/O terminal D of the cache data memory 12 is connected to the ID bus 23. The ID bus 23 is connected to the input side of the register 15. The external register 16 is connected to the output side of the register 14. The counter enable terminal CE of the control circuit 10 is activated by the control circuit 10. When the terminal CE is activated, the external register 16 stores the number of bits a (=address EA) of the cache address CA supplied from the register 14. The output side of the external register 16 is connected to both the IA bus 22 through the tri-state buffer 20 and an address terminal A of an external memory 30, which is constructed of a large-capacity, low-speed RAM or the like. The external memory 30 also has a data output terminal D, a terminal D-WAIT, and so forth as well as the address terminal A, The terminal D-WAIT outputs a signal that causes the cache memory apparatus 50 to becomes a wait state. The data output terminal D is connected to the ID bus 23 through the tri-state buffer 21, The terminal D-WAIT is connected to the input side of the control circuit 10.
FIG. 3 is a schematic diagram for explaining data stored in the cache tag memory 11. The cache tag memory 11 is constructed of addresses (tags), valid bits, and so forth. The addresses (tags) are grouped so as to reduce the hardware amount. The number of groups is referred to as the number of lines number (or the number of blocks). The adjacent addresses are normally grouped. In FIG. 3, one group has four data. For example, data with same bits except for the two low order bits are defined as one group.
Next, the operation of the cache memory apparatus 50 shown in FIG. 2 will be described.
When the cache requester 1 supplies a cache address CA to the cache memory apparatus 50, the cache address CA is temporarily stored in the register 14. Thereafter, the cache address CA is read, and it is determined whether or not data corresponding to the cache address CA is stored in the cache memory 12 (namely, whether or not a hit takes place). In other words, the accordance determining circuit 13 determines whether or not the cache address CA, which has been output from the register 14 to the IA bus 22 through the tri-state buffer 17 accords with the content of the cache tag memory 11. When they accord with each other (hereinafter this condition is referred to as hit), the accordance determining circuit 13 outputs a hit signal HIT to the control circuit 10 and the enable terminals E of the registers 14 and 15. When the hit signal HIT is input to the control circuit 10, an output signal of the control circuit 10 activates the write enable terminals WE of the cache tag memory 11 and the cache data memory 12. Thus, data designated with the low order portion (b+1) of the cache address CA is supplied from the cache data memory 12 to the ID bus 23. The data supplied to the ID bus 23 is cache data CD and output to the cache requester 1 through the register 15.
On the other hand, if the data corresponding to the cache address CA requested by the cache requester 1 does not accord (this condition is hereinafter referred to as mis-hit), the cache register 16, which is activated by the output signal of the control circuit 10, supplies the number of bits a (EA) of the cache address CA to the address terminal A of the memory 30. Thus, record data corresponding to the number of bits a is supplied from the output terminal D of the memory 30. The read data is supplied to the cache data memory 12 through the tri-state buffer 21. Thus, the content of the cache data memory 12 is updated. Thereafter, the read data is cache data CD and supplied to the cache requester 1 through the ID bus 23 and the register 15, In this case, the read data is cache data CD.
Thus, when a mis-hit takes place, data for one line including an address where the mis-hit took place is read from the external memory 30. Consequently, the content of the cache data memory 12 is updated. There are two methods for updating the content of the cache data memory 12 corresponding to the occurrence of a mis-hit and for supplying real cache data CD to the cache requester 1.